ASIC Design Verification Engineer - 98281 (Markham, Ontario, CA)

1 month ago 35
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What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

 

 

ASIC Design Verification Engineer

 

THE ROLE:

We, HW video IP team located in Markham, Ontario, Canada, are looking for a ASIC Design Verification Engineer who will work with DV architect to lead, drive, and deploy advanced verification methodology, IP infrastructure frameworks, test library and test environment in order to further improve verification efficiency and productivity.  As a member of video DV arch team, you will be responsible for shaping the future of our IP solutions with modern verification strategy and environment to drive a winning solution now and future IP generations.

 

KEY RESPONSIBILITIES:

  • Work with DV architect to define and develop new verification frameworks and test library
  • Enable re-use of C++ based models for use in architecture, functional and performance verification, and software development
  • Develop and adapt infrastructure and models to enable FPGA based hardware acceleration
  • Design and implement models and testbenches in UVM, systemC and C/C++
  • Adopt and deploy verification tool flow to enable global video teams
  • Automate and improve verification and acceleration efficiency
  • Anchor and work with global video IP teams to drive test library development among block, IP, FW and system infrastructure
  • Think outside the box!
     

PREFERRED EXPERIENCE:

  • 8+ years of hands-on experience in one or more of the following:
    • Working with ASIC design IP teams in a verification or software modeling role
    • Developing, integrating and debugging high level C++ design models (functional and performance) into simulation environments
    • Developing UVM based verification frameworks and testbenches, processes and flows
    • Automating workflows in a distributed compute environment
    • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Good working knowledge of SystemC and TLM with some related experience
  • Scripting language experience:  Perl, Ruby, Makefile, shell preferred.
  • Exposure to leadership or mentorship is an asset!
  • Desirable asset with prior exposure to video codec system or other multimedia solutions
  • Strong problem solving skills, attention to details, and result oriented performer
  • An organized, enthusiastic self-starter, strong interest in hardware verification methodologies.
  • Good interpersonal skills (verbal and written).

 

ACEDEMIC CREDENTIALS:

  • EE or Computer Engineering, or equivalent degree or above

 

#LI-EM1



Requisition Number: 98281 
Country: Canada Province: Ontario City: Markham 
Job Function:Design
 

 

AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.

 

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